RISC-V - Part 2: Ambitious Aims
The backers of the RISC-V ISA have ambitious goals. Can they achieve them?
This was not just a commercial contest, it was a battle to reclaim the soul of RISC architectures.
In RISC-V Part 1 : Origins and Architecture we looked at the origins of the RISC-V ISA and had the briefest of overviews of the instruction set.
In this post, we’re going to cover the later history of the development of RISC-V. If you’re not familiar with RISC-V then you might want to start with that earlier post.
We’ve seen that, as early as 2014, the Berkeley team who developed RISC-V had lofty ambitions for their project:
… our goal is grander: just as Linux has become the standard OS for most computing devices, we envision RISC-V becoming the standard ISA for all computing devices.
Later, we’ll see how the founders and supporters of the RISC-V project have set about achieving these ambitions. We’ll also have a very brief look at the prospects for the architecture.
It’s worth emphasising again: RISC-V is a big topic with a large, rapidly expanding and diverse ecosystem. It’s only possible to scratch the surface in a couple of posts. If you’d like to learn more then this week’s supplementary post will have suggestions for further reading.
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First Workshop and Commercialisation
When we left the story of RISC-V in Part 1 it was August 2014. The Berkeley RISC-V team, led by Krste Asanović, Yunsup Lee and Andrew Waterman, had just attended the Hot Chips 26 conference in Cupertino.
There they received a warm reception for their new ISA. Attendees liked the idea of having the freedom to use the RISC-V ISA without the restrictions associated with a licensed commercial instruction set.
With the level of interest shown at Hot Chips 26, the Berkeley RISC-V team held their first RISC-V workshop in January 2015, with over forty attendees.
There was already strong interest in the details of RISC-V, as the Berkeley team had already put a lot of material on RISC-V in the open, published on the UC Berkeley website. Yunsup Lee has recalled how, early in the project, he started to get emails from students in India, asking him to stop changing the architecture as they were already using RISC-V in their projects.
The Berkeley team soon also discovered that RISC-V was already being used in commercial projects. Asanović was surprised to hear from Mike Aronson of Rumble Systems that they had already shipped a RISC-V core in one of their products. The first RISC-V workshop also included a presentation from BlueSpec who were already developing open-source RISC-V cores.
RISC-V International
There was one concern, though, for potential early commercial users of RISC-V. They would rather not have the ISA controlled by a university research department. The interests of a research department – trying new ideas – were not necessarily consistent with their desire for the stability they needed in an instruction set architecture.
So in 2015, members of the Berkeley team set up ‘RISC-V International’, an independent foundation, registered in Delaware.
RISC-V International would oversee the governance of the ISA and help to organise the community that was growing around RISC-V. Both companies and individuals could become members of the RISC-V foundation.
The Berkeley team transferred RISC-V intellectual property, including the ISA and the distinctive blue and yellow logo, to RISC-V international.
‘Yunsup wants to do a startup’ - SiFive
With the steering of RISC-V handed over to an independent foundation, what would the original developers of the ISA do next?
Krste Asanović has recalled that Yunsup Lee was ‘very keen to do a startup’. Lee had been talking to possible investors, but ‘the more they knew about semiconductors, the faster they said no’.
Doug Mohr at Sutter Hill Ventures (SHV) had enquired about the names of promising young students at UC Berkeley. He’d been given the names of Lee and Waterman and called Lee to try to recruit him. Instead, Lee tried to get him interested in a RISC-V based startup. This in turn led to a visit to Berkeley from Stefan Dyckerhoff of SHV and to discussions about SHV backing a RISC-V based startup with Asanović, Lee and Waterman.
SiFive was incorporated in July 2015 and raised $5m seed funding from SHV, raised without a pitch deck or business plan, with SHV’s Dyckerhoff becoming interim CEO.
It took just over a year for SiFive to bring its first product to market. In November 2016, they announced a processor core, System-on-Chip and accompanying development board:
The Freedom Everywhere 310 SoC and HiFive1 development board will enable a wide variety of system architects, embedded designers, and Internet of Things providers — people who normally have to rely on chip engineers for the detailed engineering work — to create their own products.
What made the FE310 different? Well apart from using the RISC-V ISA, customers would be able to customise the design to meet their needs:
The RTL code also empowers chip designers with the ability to customize their own SoC on top of the base FE310. For system architects, developers, or companies without chip design capabilities, SiFive’s “chips-as-a-service” offering can customize the FE310 to meet their unique needs, the company said.
Nvidia and Western Digital
By 2016 there was already interest in RISC-V from large firms. Nvidia was looking to replace their in-house ‘Falcon’ cores, used to perform control and other functions in their GPUs.
After comparing several alternatives, including the Arm Cortex A53 and upgrading their own Falcon architecture, they decided instead to design their own 64-bit RISC-V core. They presented the results of the evaluation in July 2016. Alongside performance and area (<0.1mm^2) requirements, Nvidia’s Joe Xie, gave an early pointer to one of RISC-V’s key advantages:
… it's strongly preferred to be extensible because we perhaps need to optimize the ISA to be able to accelerate certain use cases …
Other companies would follow. At the end of 2018, SSD and HDD maker Western Digital announced that they were developing a series of RISC-V cores for use in their products.
In a tantalising early sign of the possibilities that an open-source ISA provided for an open RISC-V ecosystem, Western Digital open-sourced the SweRV RISC-V core in April 2019.
The SweRV Core EH1 is a 32-bit, 2-way superscalar, 9 stage pipeline core. With an expected performance of up to 5.0 CoreMarks/MHz (based on internal simulations) and small footprint, it offers compelling capabilities for embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. The power-efficient design also offers clock speeds of up to 1.8Ghz on a 28nm CMOS process technology.
The Switzerland of ISAs in Switzerland
The recent book ‘The Everything Blueprint’ by James Ashton describes the current registered address of the RISC-V Foundation in Zurich in Switzerland as “an anonymous grey office block”.
“… this venture made nothing, generated little noise from its operations and employed next to no-one locally. It had a registered address, which was a place to pick up mail, should any ever be sent, and that was about the extent of its presence”
The RISC-V foundation had moved from Delaware to Zurich in 2020. According to the RISC-V website:
Across 2018-2019, the RISC-V community has reflected on the geopolitical landscape, and we have heard concerns from around the world that investment in RISC-V must come with IP access continuity to ensure a long-term strategic investment. We first mentioned our intentions to move at the December 2018 summit. Incorporation in Switzerland has the effect of calming concerns of political disruption to the open collaboration model. RISC-V International does not maintain any commercial interest in products or services as a non-profit, membership organization. There have not been any export restrictions on RISC-V in the US, and we have complied with all US laws. The move does not circumvent any existing restrictions, but rather alleviates uncertainty going forward.
RISC-V International has not incorporated in Switzerland based on any one country, company, government, or event. This move is reflective of community concern and managing strategic risk for our community investing in RISC-V for the next 50+ years.
Arm has sometimes been described as the ‘Switzerland of semiconductors’ due to its studied neutrality. By the late 2010s, as a Japanese-owned company, registered in the UK, it looked increasingly hard for Arm to maintain that neutrality in the face of geopolitical tensions. With registration in Switzerland, a country famous for its neutrality, RISC-V was seeking to shelter from those tensions.
In 2023, the RISC-V International website says:
RISC-V does not take a political position on behalf of any geography. We are proud to see organizations from around the world working together in this new era of processor innovation.
An understandable stance perhaps, but given that early funding for RISC-V had come from the Pentagon via the ‘Defense Advanced Research Projects Agency (DARPA)’ then also a controversial one for some in the US.
Taking Aim at Arm
If RISC-V was making steady progress, then incumbents were starting to notice.
In 2018, a new website, ‘riscv-basics.com’ appeared. The website had an ‘Arm’ logo at the top and was headed ‘RISC-V Architecture: Understand the Facts’. It included a series of comparisons between arm and RISC-V, some perhaps controversial, some simple statements of fact. These were mostly points that you would expect a RISC-V competitor to make, if maybe not on a website with the ‘riscv-basics’ url.
However, the tactic soon backfired, prompting an immediate backlash. ‘The Register’ website reported soon afterwards that:
Arm told us it had hoped its anti-RISC-V site would kickstart a discussion around architectures, rather than come off as a smear attack. In any case, on Tuesday, it took the site offline by killing its DNS.
“Our intention in creating a webpage to offer key considerations around commercial RISC-V based products was to inform a lively industry debate," an Arm spokesperson told The Register.
"Regretfully, the result was something different, a page that wasn’t in line with Arm’s collaborative culture, so we’ve taken it down. Indeed, many of our own people also told us they didn’t like it.
But Arm’s website wasn’t really the first shot in the battle between the two architectures. If Asanović had been frustrated at the licensing conditions associated with using the Arm architecture, both he and his colleagues at Berkeley had long been critical of the Arm architecture itself.
In the fourth, ‘Arm-based’ edition of their famous textbook, David Patterson and John Hennessy had gone so far as to shrink the 64-bit Arm architecture down to a much smaller subset, which they named LEG (that some took semi-jokingly as an acronym for ‘Leave-out Extraneous Garbage’).
And many of the early papers from members of the Berkeley RISC-V team had been explicitly critical of the Arm architecture, in both its 32-bit and 64-bit versions, with a particular criticism that Arm isn’t as RISC-y as it might be.
(Talking about ARM64) … But many warts remain, including the use of condition codes and not-quite-general-purpose registers (the link register is implicit and, depending on the context, x31 is either the stack pointer or is hard-wired to zero). And more blemishes were added still, including a massive subword-SIMD architecture that is effectively mandatory. Overall, the ISA is complex and unwieldy: there are 1070 instructions, comprising 53 formats and eight data addressing modes, all of which takes 5,778 pages to document.
Despite the claims that ARM is a RISC ISA (it’s literally the ‘R’ in their name, after all!), ARM’s load with register offset (LDR) is just one example of how CISC-y ARM can be.
This was not just a commercial contest, it was a battle to reclaim the soul of RISC architectures.
The Berkeley RISC-V team’s own company, SiFive, would go on to set up their own research centre in Arm’s backyard, with over a hundred engineers, in Cambridge in the UK and even to sponsor the local football team Cambridge United.
If SiFive was setting up their tanks on Arm’s lawn, then by the early 2020s the incumbent would publicly admit the competitive threat from RISC-V.
In their 2021 submission to the UK’s Competition and Markets Authority (CMA) Nvidia and SoftBank set out a bullish (for RISC-V) view of RISC-V’s competitive position versus Arm. In a section that could almost be an advert for RISC-V and SiFive the document said:
RISC-V’s momentum is accelerating.
The RISC-V community is also exploiting the regulatory delay and uncertainty. The past year saw a flurry of activity in RISC-V, a threat to Arm in automotive, IoT, and SmartNICs.
In June 2021, for example, SiFive announced its “P550” high-performance CPU IP based on RISC-V, which compares favorably to Arm’s contemporary CPU IP block (Cortex-A75), in a smaller package. In December 2021, SiFive announced that its next-generation microarchitecture (available in 2022), the “P650,” which targets “high-end servers and other applications requiring large arrays of multiple processor cores.”
Established vendors are using more and more RISC-V in their offerings Renesas is partnering with SiFive to develop jointly next-generation automotive solutions, Intel is deploying RISC-V in certain FPGAs,13 and Alibaba has released open-source RISC-V processor designs.
RISC-V has two potential advantages over Arm today—it is both less expensive and more customizable than Arm. Even if customers prefer Arm today, RISC-V creates a very real competitive constraint.
The trade press is filled with the steady drumbeat of recent public announcements supporting RISC-V. SiFive announced server-class CPU IP based on RISC-V, available in 2022. At least one vendor has already produced a “demo board” for a high-performance computing server based on SiFive CPU IP.
Sophisticated firms are spending billions of dollars on RISC-V for a reason. RISC-V is a very real competitive constraint…
In truth, RISC-V is a strong competitive threat to Arm, and it is only picking up steam. RISC-V vendors are already seeing engagements in automotive and, in the years after the Transaction closes, RISC-V will gain more customers.
The rationale for emphasising the competitive threat to Arm from RISC-V was clear. It was to try to convince the CMA not to block the proposed Nvidia takeover of Arm. In the end that takeover was abandoned, but the lasting impression of RISC-V breathing down Arm’s neck remains.
V is for Venture
If SiFive had a persuasive message for its venture capital funders, then variations on that same message would work for other startups. When Krste Asanović had attended Hot Chips 26 in 2014, he’d heard stories from startup founders who had spent two years negotiating for an Arm licence. With RISC-V removing that barrier, there was an opportunity for investors to take a new interest in hardware.
At the RISC-V Summit in 2022, RISC-V International CEO Calista Redmond would claim that “We've tracked more than $2 billion in venture capital alone invested in RISC-V.”
Prominent examples of firms that would attract significant venture funding include:
- Tenstorrent: Led in 2023 by Intel and AMD veteran Jim Keller, Tenstorrent has raised over $330m to develop RISC-V based systems for both datacenters and to implement AI at the edge.
- Esperanto: With Dave Ditzel, co-author with David Patterson, of the original Berkeley RISC paper, Esperanto has raised over $120 million to develop massively parallel, energy-efficient RISC-V based chips for machine learning.
- Ventana: Over $90m raised to develop high performance RISC-V CPUs.
And, of course, not forgetting:
- SiFive: The company founded by Asanović, Lee and Waterman has raised over $360m to support its range of RISC-V cores and associated IP.
This is not to forget prominent RISC-V efforts from established firms, such as Alibaba, Imagination, Andes Technology and many others. And the investment continues with announcements made seemly almost weekly. As this post was being drafted, a new joint venture between Qualcomm and several European firms was announced.
Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor, NXP® Semiconductors, and Qualcomm Technologies, Inc., have come together to jointly invest in a company aimed at advancing the adoption of RISC-V globally by enabling next-generation hardware development.
For a more in-depth look at the RISC-V startup ecosystem, I can strongly recommend this post from
of , which sets out details of thirteen of the key firms in the RISC-V ecosystem.
RISC-V in 2023
At the 2022 RISC-V Summit, RISC-V founder Krste Asanović captured the central attraction of RISC-V:
The real reason is that the industry wants the open standard ISA business model. All the technical stuff in RISC-V is amazing, but it's really this change in the business model that makes RISC-V inevitable. And just think about this: Once you move to a high-quality open standard, you never go back to sole-source proprietary standards.
So how far has RISC-V got in the making progress towards its stated ambition? Let’s take stock of where RISC-V is in 2023.
The headlines are impressive. In 2022, RISC-V International stated that it had over 3,100 members in 70 countries, and that it estimated that over 10 billion RISC-V cores had been shipped.
‘Premier’ members of the RISC-V foundation include: Intel, Google, Alibaba Cloud, Qualcomm and Seagate. Other members include Nvidia, AMD, IBM, Meta and many, many more. Even Apple, Arm founder and developer of some of the leading Arm cores, is believed to be using RISC-V cores for some non ‘user-facing’ tasks.
When RISC-V emerged in the 2010s, there was a risk that the general purpose computing world would be dominated by just two (families of ISAs) x86 and Arm. With x86 controlled by Intel and AMD, and largely limited to desktops and servers, this would have left Arm as almost the only viable ISA choice in many other markets.
Nvidia’s failed attempt to acquire Arm demonstrates the risks associated with having such an important ISA controlled by one firm. Competition authorities were worried that Nvidia would harm competitors who relied on Arm designs.
That takeover was abandoned, Arm is on the point of being floated, and the danger of it being taken over by a major customer seems to have gone away.
Even so the emergence of RISC-V as a long-term competitor to Arm helps to provide some balance to a market that could otherwise look extremely one-sided.
In 2023, anyone with the necessary financial and technical resources can pick up the RISC-V ISA specification, develop a core or use an open-source design, and immediately have access to a wide ecosystem of compatible tools and software. The early ‘wins’ for RISC-V clearly align with the most significant benefits that this confers:
- Costs of Simple Cores: For firms using many simple cores, avoiding paying a licensing fee, can be a significant cost saving. As we have seen, Western Digital has switched to RISC-V for the millions of cores that they use in their SSDs and HDDs.
- Tailored Cores: For firms looking to heavily modify a simple core design, then RISC-V allows them then flexibility to amend that design, including by adding or removing instructions as they see fit, something that would not usually be possible with an Arm license.
Which naturally takes us on to …
- Innovative Cores: For firms looking to develop innovative cores, often coupled with accelerators, RISC-V allows them to do so.
That last opportunity takes us back to the earliest days of RISC-V when the Berkeley team coupled a RISC-V core with the Hwacha vector processor.
And RISC-V International’s move to Switzerland in 2020, may mean that the ISA will be able to avoid the current geopolitical headwinds that are affecting technology in China.
In ‘user-facing’ cores in the mainstream desktop, mobile and server markets, progress has been slower. This is in part because the software ecosystem hasn’t yet reached a place which supports the use of RISC-V in desktop and mobile platforms.
We can see signs that this is changing, though. At the 2022 Google IO Conference, a question about whether Android would support RISC-V was received with a cool ‘we're watching, but it would be a big change for us.’ By early 2023 that had changed with Google announcing that RISC-V would be a ‘tier-1’ Android architecture.
Although the roadmap was stated as needing ‘a few years’ to come to completion, the commitment to the highest quality support was clear:
‘We need to do all of the work to move from a prototype and something that runs to something that's really singing—that's showing off the best-in-class [RISC-V] processors…’
With around 3.6 billion Android phones in use around the world, a viable RISC-V Android platform could represent a huge further opportunity for the ISA and perhaps a further step towards achieving the founder’s ambitions goal.
Reader Poll
Late last week, I shared a poll to gauge Chip Letter readers’ views of the future and prospects for RISC-V. In ‘Will RISC-V become the standard for Instruction Set Architectures?’ We asked readers to choose between several options for where they see RISC-V in 20 years.
Almost 200 readers have voted so far - thank you! - and the results are ‘neck and neck’!
If you haven’t voted yet then there are still a few hours left to do so!
There are also some great and insightful comments in the comments thread, so it’s well worth a look too.
I’ll share the results in this week’s supplementary post, out on Tuesday.
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