The RISC Wars Part 1 : The Cambrian Explosion

Not just a battle between RISC and CISC, but between proliferating RISC designs.

I’d like to start this week’s post with a small confession. In last week’s post, I called Berkeley RISC-I ‘the first RISC microprocessor’. In fact, some believe that a derivative of the IBM 801, known as ROMP, was the first RISC microprocessor. The story of the 801’s successors, including ROMP, will be the subject of a later post. I believe that RISC-I deserves the title, but I should have qualified my comments in last week’s post.

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At the end of 'RISC on a Chip : David Patterson and Berkeley RISC-I', it was 1982 and David Patterson and colleagues at the University of California, Berkeley had built two working RISC microprocessors, RISC-I and RISC-II. By then, they had published papers showing that the performance of these designs exceeded that of some leading Complex Instruction Set Computer (CISC) designs, including the VAX 11/780 minicomputer.

The work at Berkeley had been supported by The Defense Advanced Research Projects Agency (DARPA) as part of their Very Large Scale Integration (VLSI) program. This support included funding work to build design tools and support a VLSI fabrication service, MOSIS.

DARPA also funded work on RISC designs at Stanford University. There, John Hennessy and his graduate students started work in early 1981 on a design known as 'MIPS', an acronym for 'Microprocessor without Interlocked Pipeline Stages'.

MIPS shared a lot of features with Berkeley RISC, but there were two important differences:

- Register windows: The MIPS design didn’t make use of register windows in the way that the Berkeley RISC designs had. Thus, registers typically needed to be saved to memory when a subroutine was called.

- Pipeline Hazards: The design didn’t have hardware to deal with pipeline hazards, for example, where pipelining means that the results of an instruction aren’t yet available for a later instruction that needs that result. Instead, the compiler was expected to deal with the hazard, an assumption that simplified the design of the MIPS processors.

As had been the case for the Berkeley RISC project, the team at Stanford published numerous papers. These again showed that RISC could outperform the leading CISC microprocessors of the day, such as the Motorola 68000. This table is from the 1982 paper, 'MIPS a Microprocessor Architecture' by John Hennessy and others:

The Berkeley and Stanford papers had now put the ideas behind RISC out in the open, and had exposed the performance that RISC designs could achieve. Naturally, interest in RISC started to grow rapidly.

Just as important as performance was the fact that they had each been built by small teams of graduate students, over a timescale of a little more than a year, and with very few bugs. If firms could reproduce this, then this would be a compelling commercial proposition. Steve Furber of Acorn computers, who would go on to develop the ARM architecture, would later say:

... the other feature of the Berkeley and Stanford stories was that they had managed to produce reasonably competitive microprocessors just using a class of graduate students for a year. So they had a lot less experience and a lot less resource than the big companies had used, and therefore we thought maybe, just maybe, with these ideas if we set off we’ll come up with something interesting possibly.

But the idea that these simple designs could outperform complex and expensive computers from major firms was not always popular. Quoting David Patterson, talking much later about the response to his and John Hennessy's work:

These were two assistant professors, not tenured faculty, who were making powerful companies very mad at them, maybe me more than John because of my personality. I think they got madder, John says they didn't get so mad at him. Now, he's president of the university. I'm still a professor. They got really, really mad at me.

This would be the start of a decades-long, sometimes acrimonious, debate about the merits of RISC vs CISC, one that continues even today.

Work on RISC at Berkeley would continue, but with a slightly different focus. Patterson and colleagues first looked to build a modified RISC design to run the Smalltalk programming language (in a project known as SOAR, for Smalltalk On A RISC) and then to form the basis of a desktop workstation (known as SPUR, for Symbolic Processing Using RISC).

The RISC Cambrian Explosion

Soon it would seem that almost everyone with an interest in semiconductor manufacturing had their own RISC design.

Here is a (non-exhaustive) list of significant RISC (or RISC derived) architectures that emerged over the second half of the 1970s and then in the 1980s (please let me know if I've missed any notable designs in the comments - I think it's very likely that I have!) The first date is the date that the project started (if known).

1975 (Working design in 1978)

IBM 801

IBM

The first fully RISC design built out of ECL integrated circuits (not a microprocessor) by a team led by John Cocke.

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1977 (Revealed publicly in 1984, first appearance in a product in 1986)

IBM ROMP

IBM

A development of the original IBM 801 project.

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1980 (Working design in 1981)

Berkeley RISC-I / RISC-II

University of California, Berkeley

DARPA funded research project by team including David Patterson.

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1981 (Working design in 1982)

Stanford MIPS

Stanford University

DARPA funded research project by team led by John Hennessy.

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1982 (Introduced in products in 1986)

PA-RISC (PA for Precision Architecture)

Hewlett Packard

Design intended to replace processors in all HP non IBM PC compatible machines.

HP PA-7000 Die Shot - byPauli Rautakorpi and published under the Creative Commons Attribution 3.0 Unported license.

(Note the galloping horse in red bottom centre)

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1982-1984

Multiple projects

Digital Equipment Corporation

Quoting Wikipedia:

Titan from DEC's Western Research Laboratory (WRL) in Palo Alto, California was a high-performance ECL based design that started in 1982, intended to run Unix.

SAFE(Streamlined Architecture for Fast Execution) was a 64-bit design that started the same year, designed by Alan Kotok (of Spacewar! fame) and Dave Orbits and intended to run VMS.

HR-32 (Hudson, RISC, 32-bit) started in 1984 by Rich Witek and Dan Dobberpuhl at the Hudson, MA fab, intended to be used as a co-processor in VAX machine.

The same year Dave Cutler started the CASCADE project at DECwest in Bellevue, Washington.

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1985

PRISM (Parallel Reduced Instruction Set Machine)

Digital Equipment Corporation

Unification of DEC's RISC efforts under the direction of Rich Witek.

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1984 (First designs available in 1985)

MIPS

MIPS Computer Systems

Commercial spin off of the Stanford MIPS project.

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1984 (First working designs in 1985)

i960

Intel Corporation

Originally joint venture with Siemens and led by Fred Pollack who was lead engineer on iAPX432.

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1984 (Releases in 1988)

AMD Am29000

Advanced Micro Devices

Design influenced by Berkeley RISC.

AMD Am29000 Die Shot By Pauli Rautakorpi - Own work, CC BY 3.0, https://commons.wikimedia.org/w/index.php?curid=29893227

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1984 (Working design in 1985)

Acorn RISC Machine (later Advanced RISC Machine or ARM)

Acorn Computers, Cambridge UK

Replacement for 6502 in BBC Micro by team led by Sophie Wilson and Steve Furber.

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1986 (Commercial release 1987)

SPARC (Scalable Processor Architecture)

Sun Microsystems

Commercial development strongly influenced by Berkeley RISC project built initially to power Sun workstations.

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1986 (First commercial release in 1990)

Power

IBM

Culmination of IBM's research projects following development of IBM 801.

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1986 (Commercial introduction)

Clipper

Fairchild / Intergraph

RISC influenced design with some more complex instructions defined in a 'Macro instruction ROM'.

Fairchild Clipper C100 Die Shot By Pauli Rautakorpi - Own work, CC BY 3.0, https://commons.wikimedia.org/w/index.php?curid=50753866

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1987 (Commercial release 1988)

88000

Motorola

Aimed at the high end market and claimed to be fastest microprocessor in the world when released.

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1988 (Commercial release 1989)

i860

Intel

First million transistor CPU which also used Very Long Instruction Word approach.

Intel i860 R Die Shot By Pauli Rautakorpi - Own work, CC BY 3.0, https://commons.wikimedia.org/w/index.php?curid=33566054

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1988

PRISM (Parallel Reduced Instruction Set Microprocessor)

Apollo

Built to power Apollo’s DN10000 workstations.

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The Death of CISC?

Perhaps just as notable as all the new RISC designs is the fact that new CISC architectures would become rare. The late 1970s had seen Intel’s 8086, the Motorola 68000, National Semiconductor  32016 and efforts from Texas Instruments and several minicomputer makers looking to shrink their designs onto VLSI. The 1980s though were notable for their absence of new CISC designs. Why would anyone commit to the bigger expense of building a new CISC architecture, when developing a, most likely faster, RISC architecture would be so much cheaper?

David Patterson himself had a hand in sealing the fate of perhaps the most complex design of the era, Intel’s iAPX432 ‘Micromainframe’ that we discussed in ‘Intel iAPX432 : Gordon Moore, Risk and Intel’s Super-CISC Failure’. IN May 1982, Patterson and others published a paper that showed the iAPX432 performing poorly against not only the VAX 11/780 but also against the first generation of 16-bit microprocessors, such as the 8086.

So had RISC already won the battle by the mid-1980s? Not entirely. CISC architectures that had a market foothold continued to be updated. Intel’s 8086 was succeeded by the 80286 and then the 80386, each offering a step change in performance and capabilities, as well as, crucially, backwards software compatibility. With Intel’s manufacturing expertise and the stranglehold that IBM compatible designs had on the business Personal Computer market, the future of the x86 architecture was assured.

Likewise, Motorola kept updating the 68000 architecture and these designs would be used in Apple’s Mac, Steve Job’s Next workstations as well as other workstations and home computers from Atari and Commodore. This was swimming against the RISC tide, though. Many CISC designs were replaced by RISC newcomers, for example in Sun workstations where the 68000 series was replaced by Sun’s own SPARC RISC processors.

The RISC Wars

But if building a new RISC chip was a low-cost and low-risk proposition in the early 1980s, then updating and ensuring that it had appropriate support would be more expensive. It was always unlikely that the market would be able to support so many RISC designs, none of which had any software compatibility with each other.

These simple RISC designs started to add more features and become more complex. They needed floating point co-processors, cache memory, more complex pipelines and so on. Plus, they had to be fabricated on increasingly expensive processes. All of this made them more expensive for firms to develop and support.

So, the question was: Who would triumph in the RISC market?

This wasn’t an easy question to answer. As the principles behind RISC were relatively simple, and the designs often had a lot in common, there was little to pick between the architectures. It was even the case now that adding new features, in the form of complex instructions, could be seen as going against the whole idea of RISC.

So it would come down to other factors. Electronics magazine in 1988 , under the headline ‘RISC Slugfest’ asked ‘Is Marketing Muscle getting more important than chip performance?’. The article went on to say that Intel and Motorola, with their established presence in the microprocessor market, would be likely to be winners in the RISC market too. One commentator quoted said:

Motorola has the top spot because of its experience, reputation, customer connections, and success with the 68000 family as well as other 8-bit processor products," she says. "The same is true of Intel. If you look at the whole RISC picture, most of the firms are not conventional microprocessor players. And the only ones now in the RISC competition recognized as long-term microprocessor innovators are Motorola and Intel. AMD comes in as a close third, but again the 29000 marks a brand-new venture for them ...

Another went on to say:

... because of the much simpler RISC architecture, the development costs to Intel and Motorola to enter this market were a small fraction of what they had to expend on their 32-bit CISC offerings. What this means is that they have even more [available resources] to devote to software support, marketing, and promotion, ...

So, who would win the battle of the RISC architectures? Would it be the incumbent microprocessor vendors like Intel and Motorola, computer manufacturers like IBM, HP or DEC, or startups like MIPS and ARM?

We'll look at how things played out and why in The RISC Wars Part 2.

This week's supplementary post, for paid subscribers, looks at how RISC technology was being portrayed in the 1980s, with an excellent article by John Markoff from Byte in 1984 and the full Electronics magazine article from 1988 quoted above.

Do you have experience with any of the now abandoned RISC architectures of the 1980s? If so, then please share your experiences in the comments.